clock-recovery circuit

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• Burst mode clock and data recovery — The passive optical network (PON) uses tree like network topology. Due to the topology of PON, the transmission modes for downstream (i.e., from optical line termination, OLT to optical network unit, ONU) and upstream (i.e., from ONU to OLT) are… …   Wikipedia

• Delay insensitive circuit — A delay insensitive circuit is a type of asynchronous circuit which performs a logic operation often within a computing processor chip. Instead of using clock signals or other global control signals, the sequencing of computation in delay… …   Wikipedia

• Phase-locked loop — PLL redirects here. For other uses, see PLL (disambiguation). A phase locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. It is an electronic… …   Wikipedia

• Jitter — For other meanings of this word, see Jitter (disambiguation). Jitter is the undesired deviation from true periodicity of an assumed periodic signal in electronics and telecommunications, often in relation to a reference clock source. Jitter may… …   Wikipedia

• Injection locking — is a high frequency (usually RF, but possibly microwave and optical) phenomenon where an oscillator directly synchronizes to another high frequency signal. In the case of a VCO an injection locking signal may override its low frequency control… …   Wikipedia

• TDMoIP — In computer networking and telecommunications, TDM over IP (TDMoIP) is the emulation of time division multiplexing (TDM) over a packet switched network (PSN). By TDM we mean a T1, E1, T3, or E3 signal, while the PSN is based either on IP or MPLS… …   Wikipedia

• Satellite modem — A satellite modem or sat modem is a modem used to establish data transfers using a communications satellite as a relay.There is a wide range of satellite modems from cheap devices for home internet access to expensive multifunctional equipment… …   Wikipedia

• Delay-locked loop — In electronics, a delay locked loop (DLL) is a digital circuit similar to a phase locked loop (PLL), with the main difference being the absence of an internal voltage controlled oscillator. A DLL can be used to change the phase of a clock signal… …   Wikipedia

• Phase detector — A phase detector is a frequency mixer or analog multiplier circuit that generates a voltage signal which represents the difference in phase between two signal inputs. It is an essential element of the phase locked loop (PLL).Detecting phase… …   Wikipedia

• Intel QuickPath Interconnect — The Intel QuickPath Interconnect (QuickPath, QPI)[1][2][3] is a point to point processor interconnect developed by Intel which replaces the Front Side Bus (FSB) in Xeon, Itanium, and certain desktop platforms. It was designed to compete with… …   Wikipedia

• Data strobe encoding — and recovered clock. Data strobe encoding (or D/S encoding) is an encoding scheme for transmitting data in digital circuits. It uses two signal lines (e.g. wires in a cable or traces on a printed circuit board), Data and Strobe. These have the… …   Wikipedia